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integrated circuit systems, inc. ICS950402 0700b?04/30/04 block diagram functionality pin configuration recommended application: amd k8 system clock with amd or via chipset output features: 2 - differential pair push-pull cpu clocks @ 3.3v 9 - pciclk (including 1 free running) @3.3v 4 - selectable pciclk/httclk @3.3v 1 - 48mhz, @3.3v fixed. 1 - 24/48mhz @ 3.3v 3 - ref @3.3v, 14.318mhz. features: programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/ write operations. uses external 14.318mhz crystal. supports hyper transport technology (httclk). amd - k8? system clock chip pll2 pll1 spread spectr um pciclk (6:0, 11) cpuclkt (1:0) cpuclkc (1:0) x1 x2 xtal osc cpu divder pci divder stop stop sdata sclk fs (3:0) 24_48sel# mode (a,b,c) pci_stop# control logic ref (2:0) 48mhz 24_48mhz / 2 pciclk_f pciclk/httclk (3:0) x 2 config. reg. cpu htt pci mhz mhz mhz 0 0 0 0 100.90 67.27 33.63 0 0 0 1 133.90 66.95 33.48 0 0 1 0 168.00 67.20 33.60 0 0 1 1 202.00 67.33 33.67 0 1 0 0 100.20 66.80 33.40 0 1 0 1 133.50 66.75 33.38 0 1 1 0 166.70 66.68 33.34 0 1 1 1 200.40 66.80 33.40 1 0 0 0 150.00 60.00 30.00 1 0 0 1 180.00 60.00 30.00 1 0 1 0 210.00 70.00 35.00 1 0 1 1 240.00 60.00 30.00 1 1 0 0 270.00 67.50 33.75 1 1 0 1 233.33 66.67 33.33 1 1 1 0 266.67 66.67 33.33 1 1 1 1 300.00 75.00 37.50 fs3 fs2 fs1 fs0 *fs0/ref0 1 48 ref1/fs1* vddref 2 47 gnd x1 3 46 vddref x2 4 45 ref2/fs2* gnd 5 44 reset# *(pciclk7/httclk0)modea 6 43 vdda *pciclk8/httclk1/modeb 7 42 gnd pciclk9/httclk2 8 41 cpuclk8t0 vddpci 9 40 cpuclk8c0 gnd 10 39 gnd pciclk10/httclk3 11 38 vddcpu pciclk11 12 37 cpuclk8t1 pciclk0 13 36 cpuclk8c1 pciclk1 14 35 vddcpu gnd 15 34 gnd vddpci 16 33 gnd ****pciclk2 17 32 vdd ****pciclk3 18 31 48mhz/fs3** vddpci 19 30 gnd gnd 20 29 avdd48 pciclk4 21 28 24_48mhz/sel24_48#*~ pciclk5 22 27 gnd ~*pciclk_f/modec 23 26 sdata ~*(pciclk6)pci_stop# 24 25 sclk 48-pin tssop/ssop * internal pull-up resistor ** internal pull-down resistor ~ this output has 2x drive strength **** this output has 2.3x drive strength ICS950402
2 ICS950402 0700b?04/30/04 pin descriptions pin # pin name pin type description 1 *fs0/ref0 i/o frequency select latch input pin / 14.318 mhz reference clock. 2 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 3 x1 in cr y stal in p ut, nominall y 14.318mhz. 4 x2 out cr y stal out p ut, nominall y 14.318mhz 5 gnd pwr ground p in. 6 *(pciclk7/httclk0)modea i/o pci clock output / hyper transport output / mode selection pin, this input is activated by the modeb selection p in. 7 *pciclk8/httclk1/modeb i/o pci clock out p ut / h yp er trans p ort out p ut / mode selection latch in p ut p in. 8 pciclk9/httclk2 out pci clock out p ut / h yp er trans p ort out p ut. 9 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 10 gnd pwr ground p in. 11 ~pciclk10/httclk3 out pci clock out p ut / h yp er trans p ort out p ut. 12 pciclk11 out pci clock out p ut. 13 pciclk0 out pci clock out p ut. 14 pciclk1 out pci clock out p ut. 15 gnd pwr ground p in. 16 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 17 ****pciclk2 out real time system reset signal for watchdog timer timeout. this signal is active low and selected b y mode latch in p ut / 3.3v pci clock clock out p ut. 18 ****pciclk3 i/o stops all pciclks besides the pciclk_f clocks at logic 0 level, when input low / pci clock out p ut , this out p ut is activated b y the mode selection p in 19 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 20 gnd pwr ground p in. 21 pciclk4 out pci clock out p ut. 22 pciclk5 out pci clock out p ut. 23 ~*pciclk_f/modec i/o free runnin g pci clock not affected b y pci_stop# / mode selection latch in p ut p in. 24 ~*(pciclk6)pci_stop# i/o pci clock output, this output is activated by the mode selection pin / stops all pciclks besides the pciclk _ f clocks at lo g ic 0 level , when in p ut low. 25 sclk in clock p in of i2c circuitr y 5v tolerant 26 sdata i/o data p in for i2c circuitr y 5v tolerant 27 gnd pwr ground pin. 28 24_48mhz/sel24_48#*~ i/o 24/48mhz clock output / latched select input for 24/48mhz output. 0=48mhz, 1 = 24mhz. 29 avdd48 pwr power for 24/48mhz out p uts and fixed pll core, nominal 3.3v 30 gnd pwr ground p in. 31 48mhz/fs3** i/o fre q uenc y select latch in p ut p in / fixed 48mhz clock out p ut. 3.3v 32 vdd pwr power su pp l y , nominal 3.3v 33 gnd pwr ground p in. 34 gnd pwr ground p in. 35 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 36 cpuclk8c1 out "com p limentar y " clocks of differential 3.3v p ush- p ull k8 p air. 37 cpuclk8t1 out "true" clocks of differential 3.3v p ush- p ull k8 p air. 38 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 39 gnd pwr ground p in. 40 cpuclk8c0 out "com p limentar y " clocks of differential 3.3v p ush- p ull k8 p air. 41 cpuclk8t0 out "true" clocks of differential 3.3v p ush- p ull k8 p air. 42 gnd pwr ground p in. 43 vdda pwr 3.3v p ower for the pll core. 44 reset# out real time system reset signal for frequency gear ratio change or watchdog timer timeout. this si g nal is active low. 45 ref2/fs2* i/o 14.318 mhz reference clock / fre q uenc y select latch in p ut p in. 46 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 47 gnd pwr ground p in. 48 ref1/fs1* i/o 14.318 mhz reference clock / frequency select latch input pin. * internal pull-up resistor ** internal pull-down resistor ~ this output has 2x drive strength **** this out p ut has 2.3x drive stren g th
3 ICS950402 0700b?04/30/04 general description the ICS950402 is a main system clock solution for desktop designs using the amd k8 cpu. it provides all necessary clock signals for clawhammer and sledgehammer systems. the ICS950402 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. power groups avdd gnd 25 crystal 29 27, 30 48mhz fixed, 32 33 fix analog, fix digital 43 42 cpu master clock, cpu analog vdd gnd 9 10 pci33_ht66outputs 16, 19 15, 20 pci33 outputs 35, 38 34, 39 cpu outputs 46 47 ref pin number description mode functionality tables modea modeb pin6 pin7 pin8 pin11 0 0 httclk0 httclk1 httclk2 pciclk10 01 modea (input only) httclk1 httclk2 httclk3 1 0 pciclk7 pciclk8 pciclk9 pciclk10 11 modea (input only) pciclk8 pciclk9 pciclk10 modec pin24 0 pciclk6 1 pci_stop#
4 ICS950402 0700b?04/30/04 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
5 ICS950402 0700b?04/30/04 table1: frequency selection table bit4 bit3 bit2 bit1 cpu htt pci vco fs3 fs2 fs1 fs0 mhz mhz mhz mhz 0000 0 100.90 67.27 33.63 403.60 0000 1 133.90 66.95 33.48 535.60 0001 0 168.00 67.20 33.60 672.00 0001 1 202.00 67.33 33.67 404.00 0 0 1 0 0 100.20 66.80 33.40 400.80 0010 1 133.50 66.75 33.38 534.00 0011 0 166.70 66.68 33.34 666.80 0011 1 200.40 66.80 33.40 400.80 0100 0 150.00 60.00 30.00 600.00 0100 1 180.00 60.00 30.00 360.00 0101 0 210.00 70.00 35.00 420.00 0101 1 240.00 60.00 30.00 480.00 0110 0 270.00 67.50 33.75 540.00 0110 1 233.33 66.67 33.33 466.66 0111 0 266.67 66.67 33.33 533.34 0111 1 300.00 75.00 37.50 600.00 1 0 0 0 0 100.00 66.67 33.33 400.00 1000 1 133.33 66.67 33.33 533.32 1001 0 166.66 66.66 33.33 666.64 1001 1 200.00 66.67 33.33 400.00 1010 0 103.00 68.67 34.33 412.00 1010 1 137.33 68.66 34.33 549.32 1011 0 171.66 68.66 34.33 686.64 1011 1 206.00 68.67 34.33 412.00 1100 0 154.50 61.80 30.90 618.00 1100 1 185.40 61.80 30.90 370.80 1101 0 216.30 72.10 36.05 432.60 1101 1 247.20 61.80 30.90 494.40 1110 0 278.10 69.53 34.76 556.20 1110 1 240.33 68.67 34.33 480.66 1111 0 274.67 68.67 34.33 549.34 1111 1 309.00 77.25 38.63 618.00 bit5
6 ICS950402 0700b?04/30/04 i 2 c table: functionality and frequency control register control function bit 7 - write disable s/w control rw disable enable 0 bit 6 - spread enable rw disable enable 0 bit 5 -fs4rw 0 bit 4 -fs3rw 0 bit 3 -fs2rw 0 bit 2 -fs1rw 0 bit 1 -fs0rw 0 bit 0 - write enable s/w control rw disable enable 0 i 2 c table: output control register control function bit 7 pciclk8/httclk1 output control rw disable enable 1 bit 6 pciclk7/httclk0 output control rw disable enable 1 bit 5 pciclk5 output control rw disable enable 1 bit 4 pciclk4 output control rw disable enable 1 bit 3 pciclk3 output control rw disable enable 1 bit 2 pciclk2 output control rw disable enable 1 bit 1 pciclk1 output control rw disable enable 1 bit 0 pciclk0 output control rw disable enable 1 i 2 c table: output control register control function bit 7 cput/c_1 output control rw disable enable 1 bit 6 cput/c_0 output control rw disable enable 1 bit 5 ref2 output control rw disable enable 1 bit 4 ref1 output control rw disable enable 1 bit 3 ref0 output control rw disable enable 1 bit 2 24_48mhz output control rw disable enable 1 bit 1 48mhz output control rw disable enable 1 bit 0 pciclk9/httclk2 output control rw disable enable 1 i 2 c table: pci free-run control register control function bit 7 pciclk11 pci_stop# control rw stoppable free run 0 bit 6 pciclk10 pci_stop# control rw stoppable free run 0 bit 5 pciclk5 pci_stop# control rw stoppable free run 0 bit 4 pciclk4 pci_stop# control rw stoppable free run 0 bit 3 pciclk3 pci_stop# control rw stoppable free run 0 bit 2 pciclk2 pci_stop# control rw stoppable free run 0 bit 1 pciclk1 pci_stop# control rw stoppable free run 0 bit 0 pciclk0 pci_stop# control rw stoppable free run 0 12 17 14 13 18 11 22 21 31 8 byte 3 pin # 1pwd - - name pin # byte 0 type 0 - - - - - - 45 21 pin # 17 byte 1 14 7 18 1 28 41/40 byte 2 48 pin # pwd 0 6 22 name type 1 name pwd name 1pwd 0 type 0 1 13 37/36 type see table1: frequency selection table
7 ICS950402 0700b?04/30/04 i 2 c table: read back and output control register control function bit 7 pciclk_f output control rw disable enable 1 bit 6 pciclk11 output control rw disable enable 1 bit 5 24_48sel - r - - 1 bit 4 fs3 - r - - 1 bit 3 fs2 - r - - 1 bit 2 fs1 - r - - 1 bit 1 fs0 - r - - 1 bit 0 pciclk10/httclk3 output control rw disable enable 1 i 2 c table: vendor and revision id register control function bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 1 i 2 c table: byte count register control function bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 i 2 c table: output control register control function bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 - - - - - - - byte 7 pin # - - pwd - type name 0 1 writin g to this re g ister will configure how many bytes will be read back, default is 0f = 15 bytes. name - - - - - - byte 6 pin # - - - - - - - - 11 byte 5 pin # name - - - - - name type byte 4 pin # 23 12 pwd type pwd pwd 1 type 0 1 revision id vendor id 0 01
8 ICS950402 0700b?04/30/04 i 2 c table: output control register control function bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 i 2 c table: watchdog timer register control function bit 7 wd7 rw - - 0 bit 6 wd6 rw - - 0 bit 5 wd5 rw - - 0 bit 4 wd4 rw - - 1 bit 3 wd3 rw - - 0 bit 2 wd2 rw - - 0 bit 1 wd1 rw - - 0 bit 0 wd0 rw - - 0 i 2 c table: vco control select bit & wd timer control register control function bit 6 wden watchdog enable rw disable enable 0 bit 7 wdrb wd alarm status bit r normal alarm x bit 4 wd sf4 rw - - 0 bit 3 wd sf3 rw - - 0 bit 2 wd sf2 rw - - 0 bit 1 wd sf1 rw - - 0 bit 0 wd sf0 rw - - 1 i 2 c table: vco frequency control register control function bit 7 n div8 n divider bit 8 rw - - x bit 6 m div6 rw - - x bit 5 m div5 rw - - x bit 4 m div4 rw - - x bit 3 m div3 rw - - x bit 2 m div2 rw - - x bit 1 m div1 rw - - x bit 0 m div0 rw - - x - - the decimal representation of m div (6:0) + 2 is equal to reference divider value. default at power up = latch-in or byte 0 rom table. - - - - - - rw disable byte 11 pin # name - type - - writing to these bit will configure the safe frequency as byte0 bit (5:1) - - - - 0 byte 10 pin # bit 7 -m/nen m/n programming enable name type enable - - these bits represent x*290ms the watchdog timer will wait before it goes to alarm mode. default is 16 x 290ms =4.64 seconds - - - - - - - - - - - pwd - - - byte 8 pin # name 1 type 0 pwd pwd pwd 1 01 1 0 type byte 9 pin # name 0
9 ICS950402 0700b?04/30/04 i 2 c table: vco frequency control register control function bit 7 n div7 rw - - x bit 6 n div6 rw - - x bit 5 n div5 rw - - x bit 4 n div4 rw - - x bit 3 n div3 rw - - x bit 2 n div2 rw - - x bit 1 n div1 rw - - x bit 0 n div0 rw - - x i 2 c table: spread spectrum control register control function bit 7 ssp7 rw - - x bit 6 ssp6 rw - - x bit 5 ssp5 rw - - x bit 4 ssp4 rw - - x bit 3 ssp3 rw - - x bit 2 ssp2 rw - - x bit 1 ssp1 rw - - x bit 0 ssp0 rw - - x i 2 c table: spread spectrum control register control function bit 7 reserved reserved r - - 0 bit 6 reserved reserved r - - 0 bit 5 reserved reserved r - - 1 bit 4 ssp12 rw - - x bit 3 ssp11 rw - - x bit 2 ssp10 rw - - x bit 1 ssp9 rw - - x bit 0 ssp8 rw - - x i 2 c table: output divider control register control function bit 7 pci / httdiv3 rw x bit 6 pci / httdiv2 rw x bit 5 pci / httdiv1 rw x bit 4 pci / httdiv0 rw x bit 3 cpu div3 rw x bit 2 cpu div2 rw x bit 1 cpu div1 rw x bit 0 cpu div0 rw x - cpu divider ratio can be configured via these 4 bits individually. see table 2: divider ratio combination table - - - pwd - pci(9:7)/htt(2:0) divider ratio can be configured via these 4 bits individually. see table 2: divider ratio combination table - - - byte 15 pin # name type - - - - - - - it is recommended to use ics spread % table for spread programming. pwd - byte 14 pin # name type - these spread spectrum bits will program the spread pecentage. it is recommended to use ics spread % table for spread programming. - - - - - - - byte 13 pin # name type type - the decimal representation of n div (8:0) + 8 is equal to vco divider value. default at power up = latch-in or byte 0 rom table. - - - - - - - byte 12 pin # name 0 01 1 1 pwd pwd 01 0
10 ICS950402 0700b?04/30/04 i 2 c table: output divider control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 reserved reserved rw - - x bit 3 pcidiv3 rw x bit 2 pcidiv2 rw x bit 1 pcidiv1 rw x bit 0 pcidiv0 rw x - pci divider ratio can be configured via these 4 bits individually. see table 2: divider ratio combination table - - - - pwd - - - type 0 1 byte 16 pin # name table 2: cpu, htt & pci divider ratio combination table bit 00 01 10 11 msb 00 0000 8 0100 4 1000 8 1100 4 01 0001 12 0101 6 1001 12 1101 6 10 0010 20 0110 10 1010 20 1110 10 11 0011 28 0111 14 1011 28 1111 14 lsb add ress di v add ress di v add ress di v add ress di v divider (3:2) divider (1:0) i 2 c table: output divider control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 httinv htt phase invert rw default inverse x bit 4 cpuinv cpu phase invert rw default inverse x bit 3 pci div3 rw x bit 2 pci div2 rw x bit 1 pci div1 rw x bit 0 pci div0 rw x i 2 c table: group skew control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 reserved reserved rw - - x bit 3 reserved reserved rw - - x bit 2 reserved reserved rw - - x bit 1 reserved reserved rw - - x bit 0 reserved reserved rw - - x - byte 18 - - - - pwd - - - name type 0 1 - - - pin # - - - - - byte 17 pin # name pwd type 0 1 pci10/httclk3 divider ratio can be configured via these 4 bits see table 2: divider ratio combination table
11 ICS950402 0700b?04/30/04 i 2 c table: group skew control register control function bit 7 pciskw3 rw 0 bit 6 pciskw2 rw 0 bit 5 pciskw1 rw 0 bit 4 pciskw0 rw 0 bit 3 pci/httskw3 rw 0 bit 2 pci/httskw2 rw 0 bit 1 pci/httskw1 rw 0 bit 0 pci/httskw0 rw 0 see table 3: 7-steps skew programming table cpu-pci(6:0) skew control cpu-pci(10:7) / htt(2:0) skew control see table 3: 7-steps skew programming table - - - - pwd - - - type - byte 19 pin # name 0 1 table 3: 7-ste p s skew pro g rammin g table 7 step 11 10 01 00 lsb 11 900 ps 750 ps 600 ps 450 ps 10 n/a n/a n/a 300 ps 01 n/a n/a n/a 150 ps 00 n/a n/a n/a 0.0 ps msb i 2 c table: group skew control register control function bit 7 reserved reserved rw - - 1 bit 6 reserved reserved rw - - 1 bit 5 reserved reserved rw - - 1 bit 4 reserved reserved rw - - 1 bit 3 reserved reserved rw - - 1 bit 2 reserved reserved rw - - 1 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 1 i 2 c table: slew rate control register pin # name control function type 0 1 pwd bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 gsr_en gearshift reset enable rw disable enable 0 bit 1 asel async frequency select rw 0 bit 0 aen async frequency enable rw 1 see table 4 for async freq - - - - - byte 21 - - - - - 01 - - - - - pwd - byte 20 pin # name type
12 ICS950402 0700b?04/30/04 i 2 c table: drive strength control register control function bit 7 pci10/htt3 drcntrl pciclk10/httclk3 drive stren g th control rw 1x 2x 1 bit 6 pci6drv pciclk6 drive strength control rw 1x 2x 1 bit 5 pci3drv pciclk3 drive strength control rw 1.2x 2.3x 1 bit 4 pci2drv pciclk2 drive strength control rw 1.2x 2.3x 1 bit 3 pcifdrv pciclk_f drive stren g th control rw 1x 2x 1 bit 2 24_48drv 24_48mhz drive stren g th control rw 1x 2x 1 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 1 i 2 c table: slew rate control register control function bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 sdrslw1 rw - - 1 bit 4 sdrslw0 rw - - 0 bit 3 pcislw1 rw - - 1 bit 2 pcislw0 rw - - 0 bit 1 pcislw1 rw - - 1 bit 0 pcislw0 rw - - 0 i 2 c table: slew rate control register control function bit 7 refslw1 rw - - 1 bit 6 refslw0 rw - - 0 bit 5 48mslw1 rw - - 1 bit 4 48mslw0 rw - - 0 bit 3 48mslw1 rw - - 1 bit 2 48mslw0 rw - - 0 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 1 24_48mhz slew rate control 01 pciclk(9:7)/httclk (2:0) slew rate control pciclk(3:0) slew rate control pciclk(11,8, 6:4) slew rate control 48mhz slew rate control - ref(2:0) slew rate control pwd - byte 24 pin # name type - - - - - - - - - - - - - pwd - byte 23 pin # name type - - 1 0 - - - - pwd - - byte 22 pin # name type 1 0 table 4: asynchronous fix pll frequency select table controlled by byte 21 bits (1:0) byte 21 byte 21 vco htt htt pci pci 48 48 ref bit 1 bit 0 freq div freq div freq div freq freq 0 0 528 8 66 8 33 11 48 14.318 0 1 main pll x main pll x main pll x 48 14.318 1 0 528 7 74.4286 7 37.7143 11 48 14.318 1 1 main pll x main pll x main pll x 48 14.318
13 ICS950402 0700b?04/30/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +3.8 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c esd protection . . . . . . . . . . . . . . . . . . . . . . . . input esd protection usung human body model > 1kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input /supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih 5ua input low current i il1 -5 ua input low current v il2 -200 ua i dd3.3op66 max loads; select @ 100mhz 171 i dd3.3op133 max loads; select @ 133mhz 183 power down pd 600 ua input frequency f i v dd = 3.3 v 12 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization 1 t stab from v dd = 3.3 v to 1% of target frequency 3ms 1 guaranteed by design, not 100% tested in production. ma input capacitance 1 operating supply current 250
14 ICS950402 0700b?04/30/04 electrical characteristics - cpuclk t a = 0 - 70c; v dd =3.3v +/- 5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance z o 1 v o =v x 50 ? output high voltage v oh2b 11.2v output low voltage v ol2b 0.4 v output low current i ol2b v ol = 0.3 v 18 ma duty cycle 1 d t2b 1 v t = 50% 45 49 52 % jitter, cycle-to-cycle 1 t j c y c-c y c2b v t = v x 0 70 200 ps v diff 1,2 0.4 1.9 2.3 v ? v diff 1 -150 80 150 mv v cm 1,2 1.45 1.6 1.85 v ? v cm 1 -200 45 200 mv notes: 1 - guaranteed by design, not 100% tested in production. 2 - test circuit: rs=15 ? , c l =5pf, vterm=100 ? between cput, cpuc differential voltage, measured @ the hammer test load (single-ended measurement) change in v diff_dc magnitude, measured @ the hammer test load (single-ended measurement) common mode voltage, measured @ the hammer test load (single-ended measurement) change in common mode voltage, measured @ the hammer test load (single-ended measurement)
15 ICS950402 0700b?04/30/04 electrical characteristics - pciclk, pcick33 / ht66 (33mhz) t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -12 ma 2.4 v output low voltage v ol1 i ol = 9.0 ma 0.4 v output high current i oh1 v oh = 2.0 v -15 ma output low current i ol1 v ol = 0.8 v 10 ma measured from 20 - 60%, 1x drive strength 0.9 0.92 2x drive strength 1.38 2.3x drive strength 1.63 measured from 60 - 20%, 1x drive strength 1.15 2x drive strength 1.93 2.3x drive strength 2.19 dut y c y cle 1 d t1 v t = 1.5 v 45 51 55 % jitter, cycle-to-cycle 1 t c y c-c y c1 measured on rising edge @ 1.5v 140 250 ps jitter, accumulated 1 -1000 450 1000 ps output impedance z o v o = v x 265 500 ps 1 guaranteed by design, not 100% tested in production. rise edge rate 1 fall edge rate 1 t r1 t f1 v/ns v/ns 1 4 4 1 electrical characteristics - pcick33 / ht66 (66mhz) t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 30 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -12 ma 2.4 v output low voltage v ol1 i ol = 9.0 ma 0.4 v output high current i oh1 v oh = 2.0 v -15 ma output low current i ol1 v ol = 0.8 v 10 ma measured from 20 - 60%, 1x drive strength 0.9 0.95 2.3x drive strength 1 1.65 measured from 60 - 20%, 1x drive strength 1.18 2.3x drive strength 2.12 dut y c y cle 1 d t1 v t = 1.5 v 45 51 55 % jitter, cycle-to-cycle 1 t c y c-c y c1 measured on rising edge @ 1.5v 200 250 ps jitter, accumulated 1 -1000 450 1000 ps output impedance z o v o = v x 265 500 ps 1 guaranteed by design, not 100% tested in production. rise edge rate 1 t r1 4v/ns v/ns fall edge rate 1 t f1 14
16 ICS950402 0700b?04/30/04 electrical characteristics - ref t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise edge rate 1 t r5 measured from 20 - 80% 0.5 1.3 2 v/ns fall edge rate 1 t f5 measured from 80 - 20% 0.5 1.5 2 v/ns duty cycle 1 d t5 v t = 50% 45 54 55 % jitter, cycle-to-cycle 1 t j c y c-c y c5 1 measured on rising edge @ 1.5v 0 190 1000 ps jitter, accumulated 1 -1000 100 1000 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 24mhz, 48mhz t a = 0 - 70c; v dd = 3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma measured from 20 - 80%, for 24_48mhz 0.5 2.35 2.5 for 48mhz 1.30 2 measured from 80 - 20%, for 24_48mhz 0.5 3.15 3.5 for 48mhz 1.65 2 duty cycle 1 d t5 v t = 50% 45 50 55 % jitter, absolute 1 t j abs5 1 v t = 1.5 v -1 0.3 1 ns jitter, cycle-to-cycle 1 t j c y c-c y c5 1 v t = v x , for 24_48mhz clock 0 200 500 ps jitter, cycle-to-cycle 1 t j c y c-c y c5 1 v t = v x , for 48mhz clock 0 260 500 ps jitter, accumulated 1 -1000 200 1000 ps output impedance z o v o = v x 20 60 ? 1 guaranteed by design, not 100% tested in production. v/ns v/ns rise edge rate 1 fall edge rate 1 t r5 t f5
17 ICS950402 0700b?04/30/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 175 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
18 ICS950402 0700b?04/30/04 ordering information ICS950402 y glf-t example: designation for tape and reel packaging lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 n d mm. d (inch) reference doc.: jedec publication 95, mo-153 0.50 basic 0.020 basic see variations see variations see variations see variations 8.10 basic 0.319 basic 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions
19 ICS950402 0700b?04/30/04 ordering information ICS950402 y flf-t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) see variations see variations 0.635 basic 0.025 basic symbol in millimeters in inches common dimensions common dimensions example: designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t

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